With the AI industry’s insatiable appetite for memory creating unprecedented supply chain bottlenecks, we are on the cusp of a major shift in memory technology. We’re joined by Dominic Jainy, a leading expert in high-performance computing and AI infrastructure, to break down a groundbreaking new partnership. We’ll explore how Intel, after decades away from the DRAM market, is teaming up with SoftBank’s Saimemory to introduce Z-Angle Memory (ZAM), a technology that promises to redefine efficiency and density. Our conversation will cover the unique Z-Angle interconnect design, the architectural innovations driving its massive power savings, and the strategic challenges Intel faces in re-establishing itself as a key player in the high-stakes memory game.
Intel is partnering with SoftBank’s Saimemory on a new ZAM technology. What specific roles will each company play in development and manufacturing, and what are the primary challenges they must overcome to bring this new memory standard to the competitive AI hardware market?
This is a fascinating symbiotic partnership. Intel is bringing its deep manufacturing expertise and foundational technology to the table, specifically the advanced DRAM bonding techniques that originated from the Department of Energy’s AMT program. You can see their hand in the use of EMIB for connectivity. SoftBank, through Saimemory, provides the strategic impetus and a potential anchor customer with its own custom ASICs, like the Izanagi lineup. This gives them a chance to control their entire hardware stack. The biggest hurdle they face is market inertia. The AI hardware world is built around HBM, and convincing giants like NVIDIA to redesign their architectures for a new memory standard, no matter how promising, is a monumental task. They’ll have to prove that ZAM’s benefits aren’t just theoretical but deliver tangible, game-changing performance in real-world applications.
The proposed Z-Angle interconnect routes connections diagonally within the die stack. Could you detail the technical advantages of this staggered topology compared to traditional HBM, and explain step-by-step how this design simplifies manufacturing while also lowering thermal resistance?
The Z-Angle approach is a genuinely clever piece of engineering that rethinks the very structure of stacked memory. Traditional HBM drills connections straight down through the silicon layers, which is complex and consumes valuable die space. The Z-Angle method, by creating a staggered, diagonal pathway, fundamentally simplifies manufacturing. Instead of perfectly aligning and drilling through an entire stack, you’re creating shorter, offset connections between layers. This diagonal route also means the heat from these interconnects is distributed more broadly across the silicon, rather than being concentrated in vertical columns, which directly contributes to lower thermal resistance and better heat dissipation. This allows for more effective use of the silicon area for the actual memory cells, leading to higher densities in the final product.
ZAM is projected to offer 40-50% lower power consumption than HBM. What specific architectural features, such as the capacitor-less design and use of EMIB, contribute to this efficiency gain? Please share some metrics on how this will impact overall system performance for large-scale AI workloads.
That 40-50% power reduction is a staggering figure, and it’s achieved through a multi-pronged architectural strategy. A core element is the capacitor-less design; removing these components from the memory cell structure eliminates a significant source of passive power draw. Then, there’s the interconnect itself. By leveraging Intel’s EMIB technology to link the memory to the AI chip, they are creating an incredibly short and efficient data path, which drastically cuts down on the energy needed to move data. For large-scale AI workloads that are constantly memory-bound, this is transformative. Lower power consumption means less heat, which in turn allows for denser server racks and lower cooling costs in data centers, directly improving the total cost of ownership for hyperscalers.
With ZAM aiming for much higher storage per chip—up to 512 GB—how does its copper-to-copper hybrid bonding enable this density? Can you explain how this creates a “monolithic-like” silicon block and what new possibilities this opens up for future AI system architecture?
The move to copper-to-copper hybrid bonding is key to achieving these incredible densities. This technique allows for a much finer pitch and more direct connection between the memory layers compared to older methods. It essentially fuses the layers together so seamlessly that the resulting stack behaves almost like a single, solid piece of silicon—what the industry calls a “monolithic-like” block. This structural integrity and efficiency are what enable stacking more layers higher and more reliably. For AI system architects, having up to 512 GB of high-bandwidth memory directly connected to a processor opens up entirely new paradigms. It means you can fit vastly larger models into a single chip’s memory, reducing the need for slower, more power-hungry communication between multiple chips or servers. This could dramatically accelerate training and inference for next-generation AI.
Given Intel’s exit from the DRAM market in 1985, what has fundamentally changed to make this re-entry viable? Beyond current supply chain bottlenecks, how might ZAM’s unique approach help Intel convince leaders like NVIDIA to adopt it over established memory solutions?
Intel’s exit in 1985 was a surrender to commodity market forces where they were outcompeted on price. What’s changed is that memory is no longer a simple commodity; for AI, it’s a critical performance enabler and a point of innovation. The current supply chain crunch has simply exposed a deeper need for new, more advanced solutions. For Intel to succeed, they can’t just offer an alternative; they must offer a revolution. ZAM’s unique value proposition—the combination of 40-50% lower power, simplified manufacturing, and unprecedented density up to 512 GB—is their Trojan horse. To convince a leader like NVIDIA, they need to demonstrate that ZAM isn’t just a better HBM, but a technology that unlocks performance that is simply impossible with existing standards. If they can prove that ZAM enables a generational leap in AI model size and efficiency, the market will have no choice but to follow.
What is your forecast for next-generation memory technologies?
I believe we are moving away from incremental improvements and into an era of architectural re-imagination. The future isn’t just about making memory faster or denser; it’s about fundamentally changing how memory integrates with processing. Technologies like ZAM, with its focus on 3D stacking, hybrid bonding, and power efficiency, are the blueprint. I foresee a future where the line between memory and compute continues to blur, leading to monolithic-style systems where massive pools of memory are fused directly with processing cores. The ultimate goal is to eliminate the data movement bottleneck entirely, and the innovations we’re seeing today are the critical first steps toward that truly unified computing architecture.