At the 2023 IEEE International Electron Devices Meeting (IEDM), Intel researchers showcased advancements in 3D stacked CMOS transistors combined with backside power and direct backside contacts. These breakthroughs in transistor architecture technology are crucial for further scaling and improved performance. In this article, we will explore the research presented by Intel’s Components Research group and their efforts to extend Moore’s Law through innovative engineering.
Intel’s Components Research Group and Engineering Boundaries
Intel’s Components Research group has consistently pushed the boundaries of engineering by exploring new possibilities in transistor technology. This group has focused on stacking transistors and taking backside power to the next level, enabling more transistor scaling and improved performance. Additionally, they have successfully demonstrated the integration of transistors made of different materials on the same wafer, opening up new possibilities for advanced transistor design.
Process Technology Roadmap and Innovation
Intel has recently announced its process technology roadmap, showcasing its innovation in continued scaling. These advancements, including PowerVia backside power, glass substrates for advanced packaging, and Foveros Direct, have originated from the work done in the Components Research group. These innovations are expected to be in production within this decade, further supporting efficient scaling and power delivery.
Key R&D Areas for Efficiently Stacking Transistors
To continue scaling efficiently, researchers have identified key areas for research and development. These areas focus on optimizing transistor stacking and utilizing backside power and backside contacts. By making advancements in these areas, significant progress can be made in transistor architecture technology, resulting in improved performance and scaling.
Intel’s Efforts to Extend Moore’s Law
Intel is dedicated to extending Moore’s Law, which states that the number of transistors on a chip doubles approximately every two years. In order to achieve this, Intel is working on improving backside power delivery and utilizing novel 2D channel materials. By leveraging these advancements, Intel aims to reach a trillion transistors on a package by 2030, enabling powerful and efficient computing.
Industry First: Vertical Stacking of CFETs
One of the most significant advancements presented by Intel at IEDM 2023 is the ability to vertically stack complementary field-effect transistors (CFETs) at a scaled gate pitch down to 60nm. This achievement marks an industry first, demonstrating Intel’s ability to push the limits of transistor design and fabrication. Vertical stacking opens up new possibilities for higher transistor density and improved performance.
Manufacturing Readiness of PowerVia
Intel’s PowerVia, a technology enabling backside power delivery, is expected to be manufacturing-ready in 2024. This implementation of backside power delivery is a significant milestone as it will enhance the efficiency and performance of future semiconductor devices. PowerVia will enable more efficient power delivery, reducing power consumption, and enabling improved device performance.
Extending and Scaling Backside Power Delivery
Intel’s Components Research group has identified paths to extend and scale backside power delivery beyond PowerVia. These innovations are key to further improving power delivery efficiency and enabling more advanced device scaling. The group is focusing on developing key process advances required to enable extended backside power delivery, setting the stage for future technological advancements.
Enablement of Area-Efficient Device Stacking
In addition to optimizing backside power delivery, Intel is also exploring the use of backside contacts and other novel vertical interconnects to enable area-efficient device stacking. By utilizing these interconnects, Intel can create more compact and efficient devices, leading to improved performance and greater transistor density. This research demonstrates Intel’s commitment to innovation in transistor architecture and efficient power delivery.
Intel’s showcase of advancements in 3D stacked CMOS transistors and backside power delivery at IEDM 2023 reaffirms their commitment to driving technology forward. As highlighted by their research and engineering breakthroughs in Components Research, Intel is continuously pushing the boundaries of innovation to support Moore’s Law and enable further scaling and efficient power delivery. The discoveries made at IEDM 2023 pave the way for exciting possibilities in future computing technologies.