Allow me to introduce Dominic Jainy, a renowned IT professional whose expertise in cutting-edge technologies like artificial intelligence, machine learning, and blockchain is matched by his deep insights into computer hardware and semiconductor advancements. Today, we’re diving into a fascinating discussion about IBM’s recently unveiled Power11 CPU, showcased at Hot Chips 2025. Dominic brings a unique perspective on how this latest architecture pushes the boundaries of performance, security, and memory capabilities. Our conversation explores the innovative design choices behind Power11, the impact of advanced packaging techniques, and what these developments mean for the future of server technology.
How did IBM’s Power11 CPU stand out at Hot Chips 2025 with its key features?
The Power11 CPU really made waves at Hot Chips 2025 with its forward-thinking design. It builds on a powerful core architecture with a wide SIMD engine, emphasizing end-to-end data bandwidth to keep the system fed with information. What’s exciting is the integration of AI acceleration, higher clock speeds up to 4.3 GHz, and significant memory uplifts with support for DDR5. On top of that, the introduction of 2.5D stacking and Quantum Safe Security positions Power11 as a future-ready solution for demanding server environments.
What led IBM to continue with an enhanced 7nm process node from Samsung for Power11 instead of adopting a smaller node like 5nm?
IBM’s decision to stick with an enhanced 7nm node was heavily influenced by client feedback. Their customers prioritized speed and performance over the density benefits of a smaller node like 5nm. By refining the 7nm process, IBM was able to extract more performance through optimizations, ensuring that Power11 delivers the kind of responsiveness and efficiency that enterprises need for their workloads.
Can you elaborate on Samsung’s iCube SI Interposer technology and its role in Power11’s 2.5D stacking?
Absolutely. Samsung’s iCube SI Interposer technology is a game-changer for Power11. It’s a packaging solution that enables 2.5D stacking, where multiple chips are placed side by side on an interposer—a kind of middle layer that facilitates high-speed connections. This setup significantly improves power delivery by reducing resistance and optimizing electrical paths. Compared to older designs, 2.5D stacking offers better thermal management and signal integrity, which are crucial for high-performance CPUs like Power11.
How does the core architecture of Power11 compare to its predecessor, Power10, in terms of design and capabilities?
Power11 maintains a similar foundational structure to Power10, with 16 cores per silicon die and a hefty 160 MB of cache. However, it pushes the envelope with scalability in dual-socket systems, ranging from 40 to 60 processor cores. The clock speeds have also been bumped up from 4.0 GHz to 4.3 GHz, which directly translates to faster processing and better handling of intensive tasks, making Power11 a substantial upgrade for performance-critical applications.
IBM emphasized thread strength and performance uplifts with Power11. Can you break down how these improvements vary across different system sizes?
Certainly. Power11 delivers impressive performance gains, but the extent varies by system size. For smaller form factors, you’re looking at a 50% performance boost, largely due to architectural tweaks and higher clock speeds that maximize efficiency in compact setups. Mid-tier systems see a 30% uplift, as they balance more cores with system complexity. High-end systems, however, show a 14% increase, which reflects the challenges of scaling performance when you’re already dealing with massive core counts and resource demands.
What can you tell us about the in-core MMA feature in Power11 and its impact on performance?
The in-core MMA, or Multiply-Matrix-Accumulator, is a specialized feature within each Power11 core designed to accelerate matrix operations, which are fundamental to AI and machine learning workloads. It boosts computational efficiency by handling these calculations directly in the core, reducing latency. Additionally, external ASICs or GPUs with Spyre Accelerators complement this by offloading specific tasks, creating a powerful synergy that enhances overall system performance for data-intensive applications.
How does the Quantum Safe Security feature in Power11 prepare it for the future of computing?
Quantum Safe Security in Power11 is a forward-looking feature aimed at protecting data against the potential threats posed by quantum computing, which could break traditional encryption methods. It’s about building cryptographic resilience into the hardware itself, ensuring that systems are secure as quantum technologies evolve. This approach mirrors security measures already implemented in IBM’s Z mainframe systems, adapting proven techniques to the Power architecture for robust protection.
Memory support seems to be a major focus for Power11. Can you walk us through the advancements in this area?
Memory is a standout area for Power11. It supports 32 DDR5 ports on a single socket, delivering four times the capacity and bandwidth of previous generations that had just 8 ports. This translates to up to 8 TB of DRAM per socket and bandwidths reaching 1200 GB/s. IBM also uses a unique DIMM form factor with copper heatsinks for better thermal performance. Plus, the system is hardware-agnostic, supporting both DDR4 and DDR5, with hints of DDR6 compatibility in future iterations, which shows they’re planning ahead.
What is your forecast for the future of server CPU architectures like Power11 in the coming years?
I’m optimistic about where server CPUs are headed. With architectures like Power11, we’re seeing a clear trend toward tighter integration of AI acceleration, advanced packaging like 2.5D stacking, and security features that anticipate emerging threats like quantum computing. I expect future iterations to push memory bandwidth even further, possibly with DDR6 becoming standard, and a stronger focus on energy efficiency to meet sustainability goals. We’ll also likely see more hybrid designs, blending general-purpose cores with specialized accelerators to tackle diverse workloads more effectively.